Povej prijatelju o tem izdelku:
Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing Katarzyna Radecka 2003 edition
Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing
Katarzyna Radecka
a
216 pages, biography
| Medij | Knjige Hardcover Book (Knjiga s trdim hrbtom in platnicami) |
| Izdano | 30. novembra 2003 |
| ISBN13 | 9781402076527 |
| Založniki | Springer-Verlag New York Inc. |
| Strani | 216 |
| Dimenzije | 155 × 235 × 14 mm · 548 g |
| Jezik | Angleščina |