A Hdl & Verilog Code: Simulated Output - Manjunatha S. - Knjige - LAP LAMBERT Academic Publishing - 9783848423248 - 21. marca 2012
Če se naslovnica in naslov ne ujemata, je naslov pravilen

A Hdl & Verilog Code: Simulated Output

Cena
€ 50,49

Naročeno iz oddaljenega skladišča

Predvidena dobava 9. - 17. jul
Dodaj na svoj seznam želja iMusic

In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between hierarchies of blocks are properly classified as netlist languages used on electric computer-aided design (CAD).

Medij Knjige     Paperback Book   (Knjiga z mehkimi platnicami in lepljenim hrbtom)
Izdano 21. marca 2012
ISBN13 9783848423248
Založniki LAP LAMBERT Academic Publishing
Strani 132
Dimenzije 150 × 8 × 226 mm   ·   215 g
Jezik Nemščina  

Ogled vseh Manjunatha S. ( Na primer Paperback Book )