Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing - Katarzyna Radecka - Knjige - Springer-Verlag New York Inc. - 9781441954022 - 7. decembra 2010
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Katarzyna Radecka
Verification by Error Modeling: Using Testing Techniques in Hardware Verification - Frontiers in Electronic Testing Softcover reprint of the original 1st ed. 2003 edition

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Na voljo tudi kot:

Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

216 pages, biography

Medij Knjige     Paperback Book   (Knjiga z mehkimi platnicami in lepljenim hrbtom)
Izdano 7. decembra 2010
ISBN13 9781441954022
Založniki Springer-Verlag New York Inc.
Strani 216
Dimenzije 155 × 235 × 12 mm   ·   331 g
Jezik Angleščina  

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Ogled vseh Katarzyna Radecka ( Na primer Hardcover Book in Paperback Book )