Gary D. Hachtel
Logic Synthesis and Verification Algorithms Gary D. Hachtel Softcover reprint of the original 1st ed. 1996 edition

Name: Logic Synthesis and Verification Algorithms
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Author: Gary D. Hachtel

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Logic Synthesis and Verification Algorithms

Gary D. Hachtel

Softcover reprint of the original 1st ed. 1996 edition

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

596 pages, biography

Medij	Knjige Paperback Book (Knjiga z mehkimi platnicami in lepljenim hrbtom)
Izdano	18. marca 2013
ISBN13	9781475770360
Založniki	Springer-Verlag New York Inc.
Strani	564
Dimenzije	178 × 254 × 31 mm · 1,03 kg
Jezik	Angleščina