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RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
| Medij | Knjige Book |
| Izdano | 10. junija 2017 |
| ISBN13 | 9781546776345 |
| Založniki | Sutherland HDL |
| Dimenzije | 150 × 220 × 20 mm · 644 g |