Design of Lna Using 0.18 Um Cmos Technology for Receiver Front End: Analysis,design and Simulation

As a distinct circuit in the receiver front end, LNA needs high gain and low Noise. This work includes the simulation results for differential topology and also improved circuit. The work is done for the frequency range of 2.45 GHz - 2.85 GHz with a central frequency of 2.65GHz. This work also demonstrate the need of on-chip inductor and capacitor design as these occupies very large silicon area. Final Simulation Results show that there is sufficient gain attained as it will reduce the Noise Figure of subsequent Circuits in Receiver Front End. Apart from voltage and power gain,simulations were done for GA, Gt etc.also,which qualifies the design. The effect of design parameters viz. Lg and Ld,for Noise and Gian respectively, have also been shown. At the end a detailed Layout of inductor is included so as to show,how much amount of silicon area it occupies. Hence,future work includes design of on-chip inductors and capacitors.