High Performance and Low Power On-die Interconnect Fabrics: Design and Challenges

Technology scaling has made billion transistors design feasible on a single die. With transistors getting cheaper and faster, the core count in multi-processor systems has been steadily increasing. High end servers, gigabit Ethernet routers and multimedia processors now serve workloads dealing with terabytes of data flow every second. Even medium throughput applications now prefer multi-core architectures over a single core implementation for better energy efficiency and fault tolerance. These system need a network to communicate data among processing and storage elements in the chip. Although processing units are getting smaller and simpler, the dramatic rise of their number in a single die has resulted in the growing complexity of interconnect. Hence, the design paradigm for multi-core chips is gradually shifting from a core-centric architecture towards an interconnect-centric architecture, where overall system performance is limited by the bandwidth of the interconnect fabric rather than the processing ability of any individual core. This work is an attempt to analyse the challenges resulting from this paradigm shift and address them with circuit and architectural innovations.