Logical Time @ Work for the Modeling and Analysis of Embedded Systems: Foundations of the Uml / Marte Time Model - Frederic Mallet - Books - LAP LAMBERT Academic Publishing - 9783843393881 - January 19, 2011
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Logical Time @ Work for the Modeling and Analysis of Embedded Systems: Foundations of the Uml / Marte Time Model

Frederic Mallet

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Logical Time @ Work for the Modeling and Analysis of Embedded Systems: Foundations of the Uml / Marte Time Model

Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.

Media Books     Paperback Book   (Book with soft cover and glued back)
Released January 19, 2011
ISBN13 9783843393881
Publishers LAP LAMBERT Academic Publishing
Pages 124
Dimensions 225 × 7 × 150 mm   ·   203 g
Language German  

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