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Cmos Low Power Analysis: Scaling Effect & Power Delay Analysis Vijay Sharma
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Cmos Low Power Analysis: Scaling Effect & Power Delay Analysis
Vijay Sharma
In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined.
| Medij | Knjige Paperback Book (Knjiga z mehkimi platnicami in lepljenim hrbtom) |
| Izdano | 1. junija 2011 |
| ISBN13 | 9783844382778 |
| Založniki | LAP LAMBERT Academic Publishing |
| Strani | 100 |
| Dimenzije | 150 × 6 × 226 mm · 167 g |
| Jezik | Nemščina |
