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Implementation of a Binary Floating Point Fused Multiply-add Unit Ahmed Hussien Khalil
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Implementation of a Binary Floating Point Fused Multiply-add Unit
Ahmed Hussien Khalil
The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy. Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.
| Medij | Knjige Paperback Book (Knjiga z mehkimi platnicami in lepljenim hrbtom) |
| Izdano | 16. decembra 2012 |
| ISBN13 | 9783846546215 |
| Založniki | LAP LAMBERT Academic Publishing |
| Strani | 104 |
| Dimenzije | 150 × 6 × 225 mm · 163 g |
| Jezik | Angleščina |