ASIC Design and Synthesis: RTL Design Using Verilog - Vaibbhav Taraate - Books - Springer Verlag, Singapore - 9789813346444 - January 8, 2022
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ASIC Design and Synthesis: RTL Design Using Verilog 1st ed. 2021 edition

Vaibbhav Taraate

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ASIC Design and Synthesis: RTL Design Using Verilog 1st ed. 2021 edition

This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.

330 pages, 184 Illustrations, color; 127 Illustrations, black and white; XXI, 330 p. 311 illus., 184

Media Books     Paperback Book   (Book with soft cover and glued back)
Released January 8, 2022
ISBN13 9789813346444
Publishers Springer Verlag, Singapore
Pages 330
Dimensions 534 g
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